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Thread: Iom IC-720A and Friends thread

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    Administrator N8YX's Avatar
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    Iom IC-720A and Friends thread

    Herein we restore, repair, modify and improve this transceiver - along with a few matching accessories.

    A number of years ago I posted in a few threads about avoiding this rig due to reliability issues with the LPF switch unit (powered by a rotary stepper motor) along with an unimpressive receiver. Time goes by, and a few amateurs devise modifications to use discrete relays to switch the various filters in and out of circuit. Also notable is Sherwood's performance data, which appears to equal or slightly best the Drake TR-7 - another favorite rig of mine. This made me want to revisit the set. eBay and a couple of Internet searches netted me three project rigs, all in various stages of (dis)repair.

    The main sticking point with all three was PLL alignment. Searches on the 'Net and through the ClassicIcom group on groups.io revealed little in the way of insight, but there was mention by a couple of hams that the documentation in the service manual was wrong in terms of what to do. Once I got the first rig up and running I applied what I learned to the others, and performed an IF Unit alignment of the first. The result...a dead-quiet receiver with no antenna connected, and one that can hear my signal generator at its lowest output on 10M.

    I'll update each reply section with pics and info as I go. Some modifications will be included - captured so they don't get lost.
    "Everyone wants to be an AM Gangsta until it's time to start doing AM Gangsta shit."

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    Administrator N8YX's Avatar
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    PLL Alignment

    The trickiest portion of the entire repair or restoration process, IMHO. Fortunately, the Front Panel, IF and RF Units can be removed to allow one to service the PLL Unit. This must also be removed, the top cover removed along with the cover over the Loop 1 oscillator section. Then reinstall in the chassis, connect up the four required cables from the Logic Unit (data - two headers on J1 and J2, power - two headers on J5 and J6), attach a frequency counter to R73 (in the Loop 1 enclosure, per the service manual) and then power the set on. Note that there's a ground wire from one corner of the Logic Unit to the main chassis. This wire MUST be connected or clip-leaded to the chassis else the Front Panel circuitry won't work correctly.

    You should see a reading of 13.300.xxxMHz on the counter if the Band Range switch is set to 'Gene' and the rig is set to 15.000.0MHz. Follow the service manual and connect a scope to Pin 12 of IC7, adjust L20/L21 for the proper square wave. Ground R41 with a clip lead. The counter should display 24.00xMHz or thereabouts. If it doesn't, carefully adjust L2 until it does. A +/-10KHz tolerance is fine.

    Note: L2, L4, L13, L18 and L19 - which will be adjusted during this process - have their cores waxed to prevent movement. Using the correct sized tool, gently turn them to break them free. If they won't budge, heat from a hot-air SMD rework pen can be used to loosen them slightly. Others have used petroleum-based solvents to remove the wax, though I would be careful using these chemicals around a plastic coil form.

    Remove the clip lead from R41, tune the set to x.001.4 and look at the indicated frequency on the counter. It should be 23.140.xxxMHz. Change to x.001.5 - the frequency should now be 13.150.xxxMHz. Both should be stable. Tune through the range of x.0015 - x.998.5 and observe the counter output. At most places it's stable. At a few there's evidence of PLL dead-banding/loss of lock.

    Here's where we throw convention and the service manual out the window. Ignore what it's telling us. Take your counter and connect it to the left terminal of J3. Turn the tuning dial to 10.998.5; USB. The counter should read 49.731.5xxMHz (or thereabouts) and should be steady. If it is, adjust C90 (next to X1) for an indicated 49.731.500MHz on the counter. If not, additional alignment work is required (detailed below).

    The manual directs one to cut a lead of R143 then check voltages at R53 and R120 - adjusting the VCO coils as necessary to achieve certain voltages - while on a specified frequency. The process is repeated by connecting the lead again, tuning another frequency and repeating the adjustment steps. R143 supplies voltage to the two VCOs if the tuning is below 11MHz and effectively adds L18 and L19 to the VCO circuits. The manual states the design logic backwards: How is doubling the inductance in an oscillator going to allow said oscillator to tune higher in frequency - all other things being equal? What I - and others - determined is that it's impossible to correctly align the PLL if you follow this procedure. (Nor is it possible to correctly align the sections if you focus on lock being a steady Loop 1 reference output, at R73).

    If the indicated frequency at J3 appears to jump around, adjust L18 (upper right VCO assembly; upper left access hole) and L19 (center VCO assembly; lower left access hole) 1/8 turn at a time until lock is obtained. (The lock tuning point is fairly sharp and you will see the indicated frequency moving up or down as the slugs are adjusted; direction of slug tuning is guided by the displayed frequency.) Once lock is achieved, use the Band Up/Down "Down" key to step downwards to 0.998.5MHz. Lock should be maintained and with each downward step the indicated MHz value should decrease by 1MHz, to 40.731.xxx or thereabouts. It should remain steady. If not, touch up L18/L19 until it's stable across the entire range.

    Next, step to 29.998.5MHz and verify lock at approximately 69.731.xxxMHz . If unstable, alternatively adjust L4 and L13 per the above procedure until lock is achieved. Step downwards through 11.998.5 and verify stability at each range, then step downwards to 10.998.5 and verify lock. Continue to 0.998.5, adjusting L18 and L19 again if need be. You may need to repeat these adjustments several times but if the circuit is otherwise working correctly, lock will be achieved. You then adjust C90 for 49.731.500MHz with the tuning set at 10.998.5MHz, as previously indicated.

    Again: The ultimate source of truth for this section is the output at J3. If it's stable across all tuning ranges, the PLL is properly in lock. I chased the 'problem' for weeks - literally - before running across commentary from others to this effect. But no one put the process to paper, so to speak.

    Note there may be a slight drift of the counter due to warm-up of the PLL Unit, but this is different from an out-of-lock unit. We'll address long-term PLL/VCO stability in a subsequent reply.
    "Everyone wants to be an AM Gangsta until it's time to start doing AM Gangsta shit."

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