The FPGA Forum - your hosts, N9XR and N1LAF

[N1LAF]

Jerry and I will lead this adventure, and everyone else can join in contribute and ask questions.

What is an FPGA?

An FPGA is Field Programmable Gate Array - it is a reprogrammable logic (also mixed with analog) device that allows the user to change the logic functions by reprogramming them, while in circuit and powered up. FPGA devices can have gate counts in the millions. Most FPGA manufacturers provide a design IDE (Integrated Design Environment) to assist the user to develop thier logic design, through schematic capture or VHDL text entry, synthesize (think optimize) and compile to a programmable file that is loaded onto the device by an external programmer. Most IDE's have simulators to allow test of your design before you implement it.

There are a number of FPGA manufacturers, including Altera, Xilinx, Lattice Semiconductor, Quicklogic, and Actel (now Microsemi). My preference is Actel, since the IDE is free.

Link to download the Actel IDE, called Libero: http://www.actel.com/download/software/libero/default.aspx

You will have to register (email address and so - they are safe), and download a one year free software license. Free every year to renew.
You will need the volume serial number of your boot drive. In Windows, the volume serial can be obtained by:

Click Start, then Run, enter CMD, hit enter
In the DOS box, enter... Vol c:
Your serial number will be returned in the box. You will need this to generate the license file on the Actel website. The license will be e-mailed to you.

Link to registration and license process: https://www.actel.com/portal/default.aspx?v=0

We will give everyone participating a week to setup, then we can proceed on the first example design, step by step. Until then, more information on FPGA's will be presented.

[NQ6U]

Thanks, Paul. Nice to be able to talk with you on something we can both agree on for a change!

Just a friendly warning to potential downloaders: it's a 902MB download (Linux version), so don't try to do it on your mobile phone or with dial-up.

[N1LAF]

Thanks, Paul. Nice to be able to talk with you on something we can both agree on for a change!

Just a friendly warning to potential downloaders: it's a 902MB download (Linux version), so don't try to do it on your mobile phone or with dial-up.

Good point. It is a BIG download, up to 2.3 GB.

Send me a DVD with return postage, and I will put record the download for those with limited download capability

[N1LAF]

FLASHPRO 4 - Programmer to program Actel chips

http://www.mouser.com/ProductDetail/Microsemi-SoC-Products/FLASHPRO4/?qs=sGAEpiMZZMt0JUFY9eAysn6larAvMUGw

$50.00

Very reasonable. USB device.

I have worked with FLASHPRO 3 programmers, easy to use.

Datasheet: http://www.actel.com/documents/FlashPro4_QS.pdf

[N1LAF]

VHDL Resources

Background and History
http://en.wikipedia.org/wiki/VHDL

Tutorial
http://esd.cs.ucr.edu/labs/tutorial/

Open source VHDL code
http://opencores.org

[N1LAF]

Actel FPGA information and datasheets
http://www.actel.com/products/pa3series/default.aspx


FPGA - Field Programmable Gate Array 20K System Gates IGLOO nano
http://www.mouser.com/_/?Keyword=Actel+FPGA&FS=True
$4.41 (Sept 2011)

[NQ6U]

There was an article on using an FPGA to implement an SDR transceiver by N2ADR in the Jan/Feb 2011 issue of QEX. He still has some issues he needs to address with his design but it's an interesting concept. I'd like to (eventually) develop an all-mode 2m rig myself since all the major manufacturers seem to have abandoned that market and, accordingly, the price of used equipment had risen to absurd levels.

[X-Rated]

I have not tried to do much except for schematic capture on this. Hey. I am a simple man.

Everything boils down to VHDL and Verilog languages. It is best to learn one. I think Verilog is most popular now. I may be wrong.

Actel (Microsemi now) is one I used mainly because they had the OTP (One time programmable) IC that could be used for the highest security situations. They have since stopped making those. Also, Atmel is another manufacturer who makes FPGA's. I am unaware if anyone makes a DIP FPGA. Most FPGA's are Ball Grid Array (BGA) or 256 pin Quad Flat Packs. If we can get enough people interested, we can do interface boards with castellations and make these fine pitch chips easy to use for the blindest of hams.

This will be an excellent read and participation deal for Ron and others who are going to undertake designs that will be long and drawn out. THESE WILL TAKE ALL OF YOUR DIGITAL DESIGN COMPONENTS AND PUT THEM INTO ONE IC. Yeah. Now that's what I am talking about.

Download the software. There are actually 2 types of software from Microsemi. I use Libero, but if your politics are different, you can choose Conservero. I think Paul uses that one and can give you more detail on that. Enough on that.

[N1LAF]

I use Libero 9.1, and I mix Schematic Capture with custom VHDL.

Not to confuse everyone, but I use OrCAD for schematic capture, and export to VHDL.

[N1LAF]

I think a multi-purpose circuit board is in order. I have a friend, and fellow ham, that runs a business in circuit board design. Bet I can get this going at cost. Maybe put a nano device inside of a PG208 package, bring out to headers, programmer connector, power supply, and include a voltage regulator for the core voltage.

[KC2UGV]

A linux IDE too :) Nice find, and looking forward to whatever other information you're coming out with :)

[X-Rated]

I think a multi-purpose circuit board is in order. I have a friend, and fellow ham, that runs a business in circuit board design. Bet I can get this going at cost. Maybe put a nano device inside of a PG208 package, bring out to headers, programmer connector, power supply, and include a voltage regulator for the core voltage.

Something along these lines is imperative if anyone here is going to get to somewhere beyond the simulator. Not many here can solder to microfine pitch flat packs, much less BGA's. That is great that you have a contact with board capabilities.

[N1LAF]

Actel (Microsemi now) is one I used mainly because they had the OTP (One time programmable) IC that could be used for the highest security situations. They have since stopped making those.

Actel now has security features for thier reprogrammable devices. The program can be encrypted, and there is a setting when programming to make the device a pass-through, where with this feature selected, you cannot reprogram it any more, nor can you erase or read from it.

[N1LAF]

Something along these lines is imperative if anyone here is going to get to somewhere beyond the simulator. Not many here can solder to microfine pitch flat packs, much less BGA's. That is great that you have a contact with board capabilities.

We can make kits out of them, with the chips installed.

[X-Rated]

We can make kits out of them, with the chips installed.

I do own a hot plate.

[N8YX]

This gives me an idea, in light of a recent purchase.

I need to build a DDS VFO and need something to control it as well as to drive a 6-digit, 7-segment (w/ DP) LED display. The device I'm thinking about using is an Analog Devices 985x-seris although others could be considered.

I/O needed:

2 lines for rotary optical encoder (quadrature stepped).

14 lines for display (7 anodes and DP plus 6 cathodes; multiplexed.)

2 lines for serial output to DDS chip. Control sequence is a 40-bit string: One QWord for setting (or getting) frequency; 8 bits of parity and EOT information.

2 lines for tuning rate: Make one "high" for fast (1khz/step), the other "high" for slow (10hz/step) and neither "high" to lock the tuning.

2 lines for "sweep" - "high" on either pin causes the DDS to tune up or down in 10KHz steps; neither "high" transfers control back to the rotary encoder.

2 lines for RIT: One for serial communications from an A/D chip (8-bit; operative range 0-FFh; center at 80h) and one for RIT Enable/Disable (high/low)

2 lines for Internal VFO Select - "high" on line 1 makes VFO1 the active VFO. "High" on line 2 makes VFO2 the active VFO. "Low" on both makes VFO1 the RX VFO and VFO2 the TX VFO.

6 lines for bandpass filter selection: Active "high" at predetermined synthesizer frequencies.

32 lines in all.

Doable?

If there are more lines available I have additional uses for them - such as computer control.

[N1LAF]

This gives me an idea, in light of a recent purchase.

I need to build a DDS VFO and need something to control it as well as to drive a 6-digit, 7-segment (w/ DP) LED display. The device I'm thinking about using is an Analog Devices 985x-seris although others could be considered.

I/O needed:

2 lines for rotary optical encoder (quadrature stepped).

14 lines for display (7 anodes and DP plus 6 cathodes; multiplexed.)

2 lines for serial output to DDS chip. Control sequence is a 40-bit string: One QWord for setting (or getting) frequency; 8 bits of parity and EOT information.

2 lines for tuning rate: Make one "high" for fast (1khz/step), the other "high" for slow (10hz/step) and neither "high" to lock the tuning.

2 lines for "sweep" - "high" on either pin causes the DDS to tune up or down in 10KHz steps; neither "high" transfers control back to the rotary encoder.

2 lines for RIT: One for serial communications from an A/D chip (8-bit; operative range 0-FFh; center at 80h) and one for RIT Enable/Disable (high/low)

2 lines for Internal VFO Select - "high" on line 1 makes VFO1 the active VFO. "High" on line 2 makes VFO2 the active VFO. "Low" on both makes VFO1 the RX VFO and VFO2 the TX VFO.

6 lines for bandpass filter selection: Active "high" at predetermined synthesizer frequencies.

32 lines in all.

Doable?

If there are more lines available I have additional uses for them - such as computer control.

How about links to the encoder, display, etc, or send me the spec sheets. How about ... Keypad entry?

[WØTKX]

Holy Moley, what an amusing device. I've been reading. My Brain Hurts. While nursing the "headache", and letting it digest, I thought... maybe this thing can do DSP? One of the biggest issues with DSP for noise reduction is the time lag, and an FPGA is pretty darn fast... I tried Google-Fu because I'm less than a novice with this stuff, and BAM!

There are a lot of "hits" for "kits". The real building is gonna be programming it. I'm just sayin', eh?

An expensive ($400) but fully packed setup, with quality audio ports and many other goodies...
http://store.altium.com/NanoBoard-3000-Series-with-Xilinx-Spartan3AN/M/B0036SF9PE.htm

Rotley wants to play asteroids in his own universe? :)
Inexpensive ($75) kit for arcade emulation...
Also used to prototype.
http://papilio.cc/index.php?n=Papilio.Papilio

Here's a "kit shop" with all kinds of pre-built choices...
Cute Digi FPGA Page (http://www.cutedigi.com/index.php?cPath=304)

[N1LAF]

Holy Moley, what an amusing device. I've been reading. My Brain Hurts. While nursing the "headache", and letting it digest, I thought... maybe this thing can do DSP? One of the biggest issues with DSP for noise reduction is the time lag, and an FPGA is pretty darn fast... I tried Google-Fu because I'm less than a novice with this stuff, and BAM!

There are a lot of "hits" for "kits". The real building is gonna be programming it. I'm just sayin', eh?

An expensive ($400) but fully packed setup, with quality audio ports and many other goodies...
http://store.altium.com/NanoBoard-3000-Series-with-Xilinx-Spartan3AN/M/B0036SF9PE.htm

Rotley wants to play asteroids in his own universe? :)
Inexpensive ($75) kit for arcade emulation...
Also used to prototype.
http://papilio.cc/index.php?n=Papilio.Papilio

Here's a "kit shop" with all kinds of pre-built choices...
Cute Digi FPGA Page (http://www.cutedigi.com/index.php?cPath=304)

There are dedicated DSP programmable devices, and can easily interface with FPGA's. I am going to go to the store for food supplies, and then I will throw some code in VHDL for some of Fred's components here, to use for examples.

If you have any questions, fire away.

[N8YX]

How about links to the encoder, display, etc, or send me the spec sheets. How about ... Keypad entry?

I will obtain that data over time and get it to you. Almost all of this stuff is 5v TTL I/O. No keypad unless the connections for such are snaked out the back of the parent transceiver. The assembly has to be a drop-in replacement for an existing unit - no hacking the front panel, please...

[N1LAF]

I will obtain that data over time and get it to you. Almost all of this stuff is 5v TTL I/O. No keypad unless the connections for such are snaked out the back of the parent transceiver. The assembly has to be a drop-in replacement for an existing unit - no hacking the front panel, please...

3.3 VDC is preferable

[N1LAF]

Something I threw together...

www.paulfelgate.com/hamisland/DisplayMux.jpg

VHDL code to follow...

What do you think, Jerry, look about right?

[X-Rated]

Something I threw together...

www.paulfelgate.com/hamisland/DisplayMux.jpg

VHDL code to follow...

What do you think, Jerry, look about right?

Watching the grandson. I will try to look it over later.

[N1LAF]

What will be really powerful is combining a PIC microcontroller with an FPGA

[N1LAF]

In the previous schematic, the segment data is stored in the DFF registers, where it is sent to the display segments. The next iteration takes binary input and convert to segment pattern to be stored in the DFF registers.

www.paulfelgate.com/hamisland/DisplayMux2.jpg
4641

[N1LAF]

This is the schematic for the Binary to Segment array

www.paulfelgate.com/hamisland/BIN2SEGA.jpg

4642

VHDL Code

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY BIN2SEGA IS PORT (
SEG : OUT std_logic_vector(7 DOWNTO 0);
B : IN std_logic_vector(7 DOWNTO 0)
);

END BIN2SEGA;



ARCHITECTURE STRUCTURE OF BIN2SEGA IS

-- COMPONENTS

COMPONENT BUF
PORT (
A : IN std_logic;
Z : OUT std_logic
); END COMPONENT;

COMPONENT NOR4
PORT (
A0 : IN std_logic;
A1 : IN std_logic;
A2 : IN std_logic;
A3 : IN std_logic;
Z : OUT std_logic
); END COMPONENT;

COMPONENT NOR6
PORT (
A0 : IN std_logic;
A1 : IN std_logic;
A2 : IN std_logic;
A3 : IN std_logic;
A4 : IN std_logic;
A5 : IN std_logic;
Z : OUT std_logic
); END COMPONENT;

COMPONENT NOR5
PORT (
A0 : IN std_logic;
A1 : IN std_logic;
A2 : IN std_logic;
A3 : IN std_logic;
A4 : IN std_logic;
Z : OUT std_logic
); END COMPONENT;

COMPONENT DEC4TO16
PORT (
Y0 : OUT std_logic;
Y1 : OUT std_logic;
Y2 : OUT std_logic;
Y3 : OUT std_logic;
Y4 : OUT std_logic;
Y5 : OUT std_logic;
Y6 : OUT std_logic;
Y7 : OUT std_logic;
Y8 : OUT std_logic;
Y9 : OUT std_logic;
Y10 : OUT std_logic;
Y11 : OUT std_logic;
Y12 : OUT std_logic;
Y13 : OUT std_logic;
Y14 : OUT std_logic;
Y15 : OUT std_logic;
A0 : IN std_logic;
A1 : IN std_logic;
A2 : IN std_logic;
A3 : IN std_logic
); END COMPONENT;

-- SIGNALS

SIGNAL Y9 : std_logic;
SIGNAL Y2 : std_logic;
SIGNAL Y13 : std_logic;
SIGNAL Y11 : std_logic;
SIGNAL Y3 : std_logic;
SIGNAL Y10 : std_logic;
SIGNAL Y6 : std_logic;
SIGNAL Y5 : std_logic;
SIGNAL Y0 : std_logic;
SIGNAL Y7 : std_logic;
SIGNAL Y12 : std_logic;
SIGNAL Y15 : std_logic;
SIGNAL Y14 : std_logic;
SIGNAL Y1 : std_logic;
SIGNAL Y4 : std_logic;

-- GATE INSTANCES

BEGIN
IOB1 : BUF PORT MAP(
A => B(7),
Z => SEG(7)
);
LG1 : NOR4 PORT MAP(
A0 => Y1,
A1 => Y4,
A2 => Y11,
A3 => Y13,
Z => SEG(0)
);
LG2 : NOR6 PORT MAP(
A0 => Y5,
A1 => Y6,
A2 => Y11,
A3 => Y12,
A4 => Y14,
A5 => Y15,
Z => SEG(1)
);
LG3 : NOR4 PORT MAP(
A0 => Y2,
A1 => Y12,
A2 => Y14,
A3 => Y15,
Z => SEG(2)
);
LG4 : NOR5 PORT MAP(
A0 => Y1,
A1 => Y4,
A2 => Y7,
A3 => Y10,
A4 => Y15,
Z => SEG(3)
);
LG5 : NOR6 PORT MAP(
A0 => Y1,
A1 => Y3,
A2 => Y4,
A3 => Y5,
A4 => Y7,
A5 => Y9,
Z => SEG(4)
);
LG6 : NOR5 PORT MAP(
A0 => Y1,
A1 => Y2,
A2 => Y3,
A3 => Y7,
A4 => Y13,
Z => SEG(5)
);
LG7 : NOR4 PORT MAP(
A0 => Y0,
A1 => Y1,
A2 => Y7,
A3 => Y12,
Z => SEG(6)
);
U2 : DEC4TO16 PORT MAP(
Y0 => Y0,
Y1 => Y1,
Y2 => Y2,
Y3 => Y3,
Y4 => Y4,
Y5 => Y5,
Y6 => Y6,
Y7 => Y7,
Y8 => OPEN,
Y9 => Y9,
Y10 => Y10,
Y11 => Y11,
Y12 => Y12,
Y13 => Y13,
Y14 => Y14,
Y15 => Y15,
A0 => B(0),
A1 => B(1),
A2 => B(2),
A3 => B(3)
);
END STRUCTURE;

[N1LAF]

A NOR4 is a four input not OR gate. The VHDL code for this is easy to understand by looking at it. The VHDL code for a NOR4 is:

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY nor4 IS
PORT (
A0 : IN std_logic;
A1 : IN std_logic;
A2 : IN std_logic;
A3 : IN std_logic;
Z : OUT std_logic
); END ENTITY;

ARCHITECTURE logic OF nor4 IS
begin
Z <= not(A0 or A1 or A2 or A3);
END logic;

[N1LAF]

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY dec4to16 is PORT (
A0 : IN std_logic;
A1 : IN std_logic;
A2 : IN std_logic;
A3 : IN std_logic;
Y0 : OUT std_logic;
Y1 : OUT std_logic;
Y2 : OUT std_logic;
Y3 : OUT std_logic;
Y4 : OUT std_logic;
Y5 : OUT std_logic;
Y6 : OUT std_logic;
Y7 : OUT std_logic;
Y8 : OUT std_logic;
Y9 : OUT std_logic;
Y10 : OUT std_logic;
Y11 : OUT std_logic;
Y12 : OUT std_logic;
Y13 : OUT std_logic;
Y14 : OUT std_logic;
Y15 : OUT std_logic
); END ENTITY;

ARCHITECTURE behavioral OF dec4to16 IS
begin
Y0 <= '1' when (A0='0' and A1='0' and A2='0' and A3='0' ) else '0';
Y1 <= '1' when (A0='1' and A1='0' and A2='0' and A3='0' ) else '0';
Y2 <= '1' when (A0='0' and A1='1' and A2='0' and A3='0' ) else '0';
Y3 <= '1' when (A0='1' and A1='1' and A2='0' and A3='0' ) else '0';
Y4 <= '1' when (A0='0' and A1='0' and A2='1' and A3='0' ) else '0';
Y5 <= '1' when (A0='1' and A1='0' and A2='1' and A3='0' ) else '0';
Y6 <= '1' when (A0='0' and A1='1' and A2='1' and A3='0' ) else '0';
Y7 <= '1' when (A0='1' and A1='1' and A2='1' and A3='0' ) else '0';
Y8 <= '1' when (A0='0' and A1='0' and A2='0' and A3='1' ) else '0';
Y9 <= '1' when (A0='1' and A1='0' and A2='0' and A3='1' ) else '0';
Y10 <= '1' when (A0='0' and A1='1' and A2='0' and A3='1' ) else '0';
Y11 <= '1' when (A0='1' and A1='1' and A2='0' and A3='1' ) else '0';
Y12 <= '1' when (A0='0' and A1='0' and A2='1' and A3='1' ) else '0';
Y13 <= '1' when (A0='1' and A1='0' and A2='1' and A3='1' ) else '0';
Y14 <= '1' when (A0='0' and A1='1' and A2='1' and A3='1' ) else '0';
Y15 <= '1' when (A0='1' and A1='1' and A2='1' and A3='1' ) else '0';
END behavioral;

[N1LAF]

Quadrature Decoding in FPGA's

http://www.fpga4fun.com/QuadratureDecoder.html

[N1LAF]

Anyone downloaded the Actel IDE?

Any Interest?

[NQ6U]

I downloaded the Linux version (so I can use in on the laptop, which dual boots OS X and Ubuntu), but haven't installed it yet. The schematics you've posted are still over my head but I've been reading up a bit to try and understand FPGAs a bit better.

[N1LAF]

I downloaded the Linux version (so I can use in on the laptop, which dual boots OS X and Ubuntu), but haven't installed it yet. The schematics you've posted are still over my head but I've been reading up a bit to try and understand FPGAs a bit better.

Take some time to install the software, and by next weekend we will go through a simple example. Build from there.

[NQ6U]

I installed the software but can't figure out how to launch it! No GUI version that I can see and the usual Terminal CLI prompts don't work either.

[N1LAF]

I installed the software but can't figure out how to launch it! No GUI version that I can see and the usual Terminal CLI prompts don't work either.

Having seen Linux, it can be a mess, like any other Linux program. If Windows, it would be easy

The Actel Libero IDE looks like this...

4649

[N1LAF]

Here is an example of a 3 to 8 decoder, with an enable line. If the enable is high, all outputs are high. If enable is low, then one of the eight outputs will be low corresponding to the three inputs A0, A1, and A2. Enable is g0. Outputs Y0 to Y7

VHDL Code for ndec3to8g0

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY ndec3to8g0 is PORT (
A0 : IN std_logic;
A1 : IN std_logic;
A2 : IN std_logic;
g0 : IN std_logic;
Y0 : OUT std_logic;
Y1 : OUT std_logic;
Y2 : OUT std_logic;
Y3 : OUT std_logic;
Y4 : OUT std_logic;
Y5 : OUT std_logic;
Y6 : OUT std_logic;
Y7 : OUT std_logic
); END ENTITY;

ARCHITECTURE behavioral OF ndec3to8g0 IS
begin
Y0 <= '0' when (A0='0' and A1='0' and A2='0' and g0='0' ) else '1';
Y1 <= '0' when (A0='1' and A1='0' and A2='0' and g0='0' ) else '1';
Y2 <= '0' when (A0='0' and A1='1' and A2='0' and g0='0' ) else '1';
Y3 <= '0' when (A0='1' and A1='1' and A2='0' and g0='0' ) else '1';
Y4 <= '0' when (A0='0' and A1='0' and A2='1' and g0='0' ) else '1';
Y5 <= '0' when (A0='1' and A1='0' and A2='1' and g0='0' ) else '1';
Y6 <= '0' when (A0='0' and A1='1' and A2='1' and g0='0' ) else '1';
Y7 <= '0' when (A0='1' and A1='1' and A2='1' and g0='0' ) else '1';
END behavioral;

VHDL Code linked to Actel Libero, and Synthesized. No errors.


4650

4651


I will construct a testbench, and then run the simulator next

[N1LAF]

I created the testbench file, and added it to the Libero IDE.

4652

Then, ran the simulator

4653


Notice that there are some glitches. This is normal considering time deltas of gates changing states with relations to inputs. Output of decoders should be used with care. That is where the enable line comes in - more on this later.


Here is the test bench file for this simple example...

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS

COMPONENT ndec3to8g0 PORT(
Y0 : OUT std_logic;
Y1 : OUT std_logic;
Y2 : OUT std_logic;
Y3 : OUT std_logic;
Y4 : OUT std_logic;
Y5 : OUT std_logic;
Y6 : OUT std_logic;
Y7 : OUT std_logic;
A0 : IN std_logic;
A1 : IN std_logic;
A2 : IN std_logic;
g0 : IN std_logic
); END COMPONENT;


SIGNAL Y0 : std_logic;
SIGNAL Y1 : std_logic;
SIGNAL Y2 : std_logic;
SIGNAL Y3 : std_logic;
SIGNAL Y4 : std_logic;
SIGNAL Y5 : std_logic;
SIGNAL Y6 : std_logic;
SIGNAL Y7 : std_logic;
SIGNAL A0 : std_logic;
SIGNAL A1 : std_logic;
SIGNAL A2 : std_logic;
SIGNAL g0 : std_logic;

BEGIN

UUT : ndec3to8g0 PORT MAP(
Y0 => Y0,
Y1 => Y1,
Y2 => Y2,
Y3 => Y3,
Y4 => Y4,
Y5 => Y5,
Y6 => Y6,
Y7 => Y7,
A0 => A0,
A1 => A1,
A2 => A2,
g0 => g0
);
-- testbench starts here --
tb : PROCESS
BEGIN

A0 <= '0';
A1 <= '0';
A2 <= '0';
g0 <= '0';
wait for 30 ns;

A0 <= '1';
A1 <= '0';
A2 <= '0';
g0 <= '0';
wait for 30 ns;

A0 <= '0';
A1 <= '1';
A2 <= '0';
g0 <= '0';
wait for 30 ns;

A0 <= '1';
A1 <= '1';
A2 <= '0';
g0 <= '0';
wait for 30 ns;


A0 <= '0';
A1 <= '0';
A2 <= '1';
g0 <= '0';
wait for 30 ns;

A0 <= '1';
A1 <= '0';
A2 <= '1';
g0 <= '0';
wait for 30 ns;

A0 <= '0';
A1 <= '1';
A2 <= '1';
g0 <= '0';
wait for 30 ns;

A0 <= '1';
A1 <= '1';
A2 <= '1';
g0 <= '0';
wait for 30 ns;



A0 <= '1';
A1 <= '1';
A2 <= '1';
g0 <= '1';
wait for 30 ns;



A0 <= '1';
A1 <= '1';
A2 <= '1';
g0 <= '0';
wait for 30 ns;


WAIT;
END PROCESS;
END;

[N1LAF]

Here is another run, where the g0 enable line is strobed at a time different than the changing A0 - A2. Note that the glitches are gone. This decoder, using A0, A1, and A2 as address lines, the data strobe is used on the enable line. Now we can strobe storage registers according to the address as represented by A0, A1, and A2.

4654

Testbench file for this run...

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS

COMPONENT ndec3to8g0 PORT(
Y0 : OUT std_logic;
Y1 : OUT std_logic;
Y2 : OUT std_logic;
Y3 : OUT std_logic;
Y4 : OUT std_logic;
Y5 : OUT std_logic;
Y6 : OUT std_logic;
Y7 : OUT std_logic;
A0 : IN std_logic;
A1 : IN std_logic;
A2 : IN std_logic;
g0 : IN std_logic
); END COMPONENT;


SIGNAL Y0 : std_logic;
SIGNAL Y1 : std_logic;
SIGNAL Y2 : std_logic;
SIGNAL Y3 : std_logic;
SIGNAL Y4 : std_logic;
SIGNAL Y5 : std_logic;
SIGNAL Y6 : std_logic;
SIGNAL Y7 : std_logic;
SIGNAL A0 : std_logic;
SIGNAL A1 : std_logic;
SIGNAL A2 : std_logic;
SIGNAL g0 : std_logic;

BEGIN

UUT : ndec3to8g0 PORT MAP(
Y0 => Y0,
Y1 => Y1,
Y2 => Y2,
Y3 => Y3,
Y4 => Y4,
Y5 => Y5,
Y6 => Y6,
Y7 => Y7,
A0 => A0,
A1 => A1,
A2 => A2,
g0 => g0
);
-- testbench starts here --
tb : PROCESS
BEGIN

A0 <= '0';
A1 <= '0';
A2 <= '0';
g0 <= '1';
wait for 30 ns;
g0 <= '0';
wait for 30 ns;
g0 <= '1';
wait for 30 ns;

A0 <= '1';
A1 <= '0';
A2 <= '0';
wait for 30 ns;
g0 <= '0';
wait for 30 ns;
g0 <= '1';
wait for 30 ns;

A0 <= '0';
A1 <= '1';
A2 <= '0';
wait for 30 ns;
g0 <= '0';
wait for 30 ns;
g0 <= '1';
wait for 30 ns;

A0 <= '1';
A1 <= '1';
A2 <= '0';
wait for 30 ns;
g0 <= '0';
wait for 30 ns;
g0 <= '1';
wait for 30 ns;


A0 <= '0';
A1 <= '0';
A2 <= '1';
wait for 30 ns;
g0 <= '0';
wait for 30 ns;
g0 <= '1';
wait for 30 ns;

A0 <= '1';
A1 <= '0';
A2 <= '1';
wait for 30 ns;
g0 <= '0';
wait for 30 ns;
g0 <= '1';
wait for 30 ns;

A0 <= '0';
A1 <= '1';
A2 <= '1';
wait for 30 ns;
g0 <= '0';
wait for 30 ns;
g0 <= '1';
wait for 30 ns;

A0 <= '1';
A1 <= '1';
A2 <= '1';
wait for 30 ns;
g0 <= '0';
wait for 30 ns;
g0 <= '1';
wait for 30 ns;




WAIT;
END PROCESS;
END;

[N1LAF]

I installed the software but can't figure out how to launch it! No GUI version that I can see and the usual Terminal CLI prompts don't work either.

From the Actel website...

Installation Instructions:

Log in with read/write permission to system on which Libero IDE Linux will be installed.
Download LiberoLU91_Lin.bin.gz.
To unzip the file, you must have read/write permission on the file.
To add read/write permission, type chmod +rw LiberoLU91_Lin.bin.gz.
Then, type gunzip ./LiberoLU91_Lin.bin.gz
To run Setup, add execute permission to the filename.
To add execute permission, type chmod +x LiberoLU91_Lin.bin.gz
To run Setup in GUI mode, type ./LiberoLU91_Lin.bin (GUI install is the default setting.)
To run Setup in batch/console mode, type ./LiberoLU91_Lin.bin -i console
Do not run Setup by clicking setup in File Manager.

[NQ6U]

Yeah, I got it installed but when I try to launch it from the command line [./usr/local/Actel/Liberos/bin/Liberos I think was the path), I get an error message telling me that a Motif Library is missing. I guess I have to try and go find that now.

Things like that are what's going to keep Linux from ever being a mainstream desktop OS.

[N1LAF]

Yeah, I got it installed but when I try to launch it from the command line [./usr/local/Actel/Liberos/bin/Liberos I think was the path), I get an error message telling me that a Motif Library is missing. I guess I have to try and go find that now.

Things like that are what's going to keep Linux from ever being a mainstream desktop OS.

Exactly.

Do you find the example here of interest? Any questions?

[mw0uzo]

Ok I'm interested :)
Downloading linux version now.

[NQ6U]

Ok I'm interested :)
Downloading linux version now.

Hope you have better luck with it than I have. I found the Motif libraries and installed them. Progress was made—I now get a different set of error messages in the terminal window when the launch fails.

[K7SGJ]

Hope you have better luck with it than I have. I found the Motif libraries and installed them. Progress was made—I now get a different set of error messages in the terminal window when the launch fails.

Probably a good thing you didn't work for NASA.

[NQ6U]

Probably a good thing you didn't work for NASA.

I Agree With You Completely.

[KC2UGV]

Yeah, I got it installed but when I try to launch it from the command line [./usr/local/Actel/Liberos/bin/Liberos I think was the path), I get an error message telling me that a Motif Library is missing. I guess I have to try and go find that now.

Things like that are what's going to keep Linux from ever being a mainstream desktop OS.

sudo apt-get install libmotif-dev

[KC2UGV]

Hope you have better luck with it than I have. I found the Motif libraries and installed them. Progress was made—I now get a different set of error messages in the terminal window when the launch fails.

What are the errors?

You can't blame the OS. The blame goes to the package creator. If it were a package built specifically for your system, then all the setup would be done for you :)

[N1LAF]

Corey, you think you can get the Actel Libero to run on Linux?

Any questions on the example I gave here?

[KC2UGV]

Corey, you think you can get the Actel Libero to run on Linux?


I'm popping up a VM now to give it a whirl (Just getting the chance).



Any questions on the example I gave here?

Not yet... But just wait, I'm sure I'll have a bunch :)

[N1LAF]

Corey, did you get the program to run on Linux yet??

[KC2UGV]

Automated provisioning is down, so I'm doing the old-school method of a linux deployment... Taking a lot longer due to downloads. Will give status, and how to, for ubuntu this afternoon.

Maybe this weekend, I'll get a chance to try it out on CentOS or Scientific Linux.

[KC2UGV]

These downloads are like x-box huge... And you need to download a total of 1.6 GB in order to get started with the most up-to-date version...

Sigh... Getting there.

[N1LAF]

These downloads are like x-box huge... And you need to download a total of 1.6 GB in order to get started with the most up-to-date version...

Sigh... Getting there.

How goes the progress?

Anyone else set up this program? Program setup painless in the Windows version....

[mw0uzo]

Got it downloaded, but no time to install yet :/

[X-Rated]

I too need more time to sit down and go through the installation processes. It is far more complicated than what it was a few years ago.

[N1LAF]

Just the basic install will do. Then need to get the license.

Here is something I have been doing as an example, it is a SPI (Serial Peripheral Interface), a synchronous serial interface.

4688

http://paulfelgate.com/hamisland/spim8.jpg

The serial lines are SEN (Serial Enable, active low), SCK(Serial Clock), SDI (Serial Data Input), and SDO (Serial Data Output).
Data to send to SPI is DIN, and the data from the SPI is DOUT

On SPI serial, the data transfer starts with the SEN line goes low. The first data bit is put on the SDO line, When the SCK goes from low to high, it tells the serial client device to latch the data bit. At the same time, the SPI master device reads the SDI serial input bit from the client device. The client device also releases the first data bit when SEN goes low. When the SCK goes from high to low, the data bit is shifted in to the serial to parallel register, and the next bit is shifted out to the SDO line. This process repeats until all data is transferred, and SEN goes high. When SEN goes high, the shifted data input is latched for output, DOUT. DIN is also latched for the next transfer.

[N1LAF]

Did the Actel software install scare everyone away?!?!?

[KC2UGV]

Did the Actel software install scare everyone away?!?!?

It's installed... Just figuring out what needs to run now. It's having an issue finding it's own libraries :/

[X-Rated]

I hope no one gets scared away. If I can do this stuff, you will see it is pretty elementary. A worker in Singapore emailed me a few months back about a design I did over 6 years ago that they are still manufacturing. I haven't worked there in 5 years now.

[N1LAF]

It's installed... Just figuring out what needs to run now. It's having an issue finding it's own libraries :/

Not an issue with Windows install. The Actel website indicates the Linux of choice is Redhat... but nothing says it couldn't work with another variant...

[N1LAF]

Record your boot/program drive volume serial number (xxxx-xxxx), you will need this for the free license registration, at this link:
https://www.actel.com/portal/default.aspx?r=1

When your license file has been generated, and you have downloaded it, save it to a folder like... C:\Actel\License
The filename of the license will be: license.dat

The environment variables may need to be set for this, as explained in the license help document:
http://www.actel.com/documents/license_troubleshooting_FAQ.pdf

Let me know when installed and licensed...

[X-Rated]

Record your boot/program drive volume serial number (xxxx-xxxx), you will need this for the free license registration, at this link:
https://www.actel.com/portal/default.aspx?r=1

When your license file has been generated, and you have downloaded it, save it to a folder like... C:\Actel\License
The filename of the license will be: license.dat

The environment variables may need to be set for this, as explained in the license help document:
http://www.actel.com/documents/license_troubleshooting_FAQ.pdf

Let me know when installed and licensed...

I am trying to download this stuff this evening again. I gave up on using Firefox and went with IE. IE did hang for about a half hour and started working again with this stuff. But I think it had to do with allowing pop ups. Then I told it to give me all of the tools and all of the Igloo instances as well. So this is not a real easy thing to do for me. I am using Vista here on this laptop.

I will keep you updated.

[KC2UGV]

Not an issue with Windows install. The Actel website indicates the Linux of choice is Redhat... but nothing says it couldn't work with another variant...

Yeah, wiping this instance and loading up CentOS (Don't have my RHEL DVD's handy)... Going to try this one more 'gain...

[N1LAF]

VHDL References

Those with programming language skills will pick up fast with this.

References:
Wikipedia VHDL background: http://en.wikipedia.org/wiki/VHDL
A Reference Manual: http://www.usna.edu/EE/ee462/manuals/vhdl_ref.pdf
http://webdocs.cs.ualberta.ca/~amaral/courses/329/labs/VHDL_Reference.html
http://ecad.tu-sofia.bg/soc/data/vhdl/vhdl_golden_reference_guide.pdf
http://www.doulos.com/knowhow/vhdl_designers_guide/

Tutorial:
http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html

Intermediate Examples:
http://www.cs.umbc.edu/portal/help/VHDL/samples/samples.html

[N1LAF]

Five input AND gate code


----------------------- VHDL CODE ---------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY AND5 IS
PORT (
A0 : IN std_logic;
A1 : IN std_logic;
A2 : IN std_logic;
A3 : IN std_logic;
A4 : IN std_logic;
Z : OUT std_logic
);
END ENTITY;

ARCHITECTURE logic OF AND5 IS

begin
Z <= A0 and A1 and A2 and A3 and A4;
END logic;

-------------------------------------------------------

ENTITY describes what the inputs and outputs are. Order independent. Similar to a function call.
Signals have one of three properties, IN, OUT, and INOUT (bidirectional)

The ARCHITECTURE is how the function behaves.

[n2ize]

sudo apt-get install libmotif-dev

Yes... excellent point. All too often things don;t work as planned because people forget to install the "dev" packages that contain the needed libraries, header files, etc. These days its almost routine for me to include the "dev" package along with every package I install.

[N1LAF]

Anyone ready to go with this?

[X-Rated]

Anyone ready to go with this?

http://openhpsdr.org/

This provides for a forum for the FPGA related amateur exchanges.

Thank you.

[N1LAF]

Actel has been acquired by Microsemi, but the products are still the same. I also found those who worked for Lattice Semiconductor, now work for Microsemi. For me, Microsemi and Actel are interchangeable.

Looks like Mouser no longer carries Actel devices, so you can go to Digikey, another fine parts distributor, for your Actel parts needs.
Devices: http://search.digikey.com/us/en/cat/integrated-circuits-ics/embedded-fpgas-field-programmable-gate-array/2556262?k=Actel

The FLASHPro 4 Programmer is also available at Digikey
http://parts.digikey.com/1/parts/2516947-programmer-flash-fpga-flashpro4.html

You can also get a DevKit with a programmer here:
http://search.digikey.com/scripts/DkSearch/dksus.dll?WT.z_supplier_id=1100&WT.z_page_type=SP&WT.z_page_sub_type=SS&WT.z_oss_type=Keyword&v=1100&lang=EN&site=us&KeyWords=er%09AGLN-NANO-KIT&x=13&y=10

Details here:
http://www.actel.com/products/hardware/devkits_boards/igloonano_starter.aspx


The development software is found here:
http://www.actel.com/download/software/liberoide/default.aspx
Click here --> Download Libero IDE v9.1 for Windows, http://www.actel.com/download/software/libero/files.aspx?os=WIN

Free license, good for 1 year, renew free every year, but will have to register....
https://www.actel.com/portal/default.aspx?r=1

During the license procedure, it will ask you for your Drive C volume number
Click on Start, then Run, enter 'cmd' and and click 'OK'
In the CMD window, enter "Vol c:"
the volume number is returned
xxxx-xxxx

This number is needed for registration.

They will e-mail you the license file and have instructions on license install. Most likely, you will have to enter

[ab1ga]

Paul, I couldn't participate the first time, but I'm in this time around.
I'm going to order the IGLOO kit tomorrow, and review the tutorials and documents posted earlier while it's in transit.
I warn you, I'm a bit slow on the uptake, so baby steps will need to be the order of the day at the start.
Thanks for reviving the thread, I've had a project in mind for months and an FPGA would be a fun implementation approach.

73,

[N1LAF]

First step while waiting for the hardware/Dev kit, is to load the Libero software. After the software is installed, then we can perform simple exercises to break into the FPGA/VHDL learning cycle, easy to do examples and simple logic. It will grow from there.

In the past, I had mentioned using a PIC microcontroller with an FPGA, any other candidate devices that may be a good fit for FPGA's?

[ab1ga]

First step while waiting for the hardware/Dev kit, is to load the Libero software. After the software is installed, then we can perform simple exercises to break into the FPGA/VHDL learning cycle, easy to do examples and simple logic. It will grow from there.

In the past, I had mentioned using a PIC microcontroller with an FPGA, any other candidate devices that may be a good fit for FPGA's?

OK, will start that tomorrow. Main box here is Win7 64-bit, I'll report any snags.

For chips that may be a good fit, one possibility is Parallax Propeller. Available in 40 pin DIP (!) or QFP, it also has low cost learning kits/dev kits. Good function libraries, mostly user-written. But if I read the data sheets correctly, the Altec chip in the IGLOO DevKit has an ARM Cortex M1 processor, so the FPGA may really be all you need except for some I/O circuitry.

Bed time. G'night all.

[ab1ga]

Paul,

Got the license, but folks should be aware of some "gotchas".

1. Get the volume number from C: before starting, it makes things a bit simpler.

2. When registering for the license, you have to give your name, email, etc. which is fine. The form also requires a company name, phone number, job title, and market served. Just a heads up, when you register you'll become a marketing target, which can be a nuisance.

3. Now a decision point. Libero now comes in two flavors. Libero IDE will continue to be updated, but only for legacy products, not for new chip families. Libero SoC 10.0 will be the new flagship software, and it's the one that's going to support the IGLOO chips. The user interface of LiberoSoC is NOT the same as Libero IDE.

Which to get? I'd like to buy the IGLOO DevKit because it has a programmer and a lot of support circuitry on board, which will remove the need to have a board made. The price is good, too, at $110 for the whole bit. The drawback is that you'd be working with a new interface, which means you'd have to learn the interface while teaching us, and I don't want to shovel more work at you without your concurrence.

Suggestion? Preference?

73,

[N1LAF]

That Propeller device is pretty cool, lots of support too.
http://www.parallax.com/PropellerChips/tabid/833/Default.aspx

The Actel device does have the Cortex Arm 7 microcontroller built into some of their products, and they can be a little pricey. You can get a PIC for < $10.

[N1LAF]

Run LiberoSoC, select New Project from the upper left menu box.

Project name: Decoder
Location: C:\projects\FPGA\

and click OK

In the C:\Projects\FPGA\Decoder\hdl folder, create a new text file


Copy the following VHDL Code in that text file, and save it as decoder.vhd
Double-click on decoder.vhdl, select choose program, and select wordpad. Use wordpad as default program always.

-- vhdl code for decoder
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY dec3to8g0 is PORT (
A0 : IN std_logic;
A1 : IN std_logic;
A2 : IN std_logic;
g0 : IN std_logic;
Y0 : OUT std_logic;
Y1 : OUT std_logic;
Y2 : OUT std_logic;
Y3 : OUT std_logic;
Y4 : OUT std_logic;
Y5 : OUT std_logic;
Y6 : OUT std_logic;
Y7 : OUT std_logic
); END ENTITY;

ARCHITECTURE behavioral OF dec3to8g0 IS
begin
Y0 <= '1' when (A0='0' and A1='0' and A2='0' and g0='0' ) else '0';
Y1 <= '1' when (A0='1' and A1='0' and A2='0' and g0='0' ) else '0';
Y2 <= '1' when (A0='0' and A1='1' and A2='0' and g0='0' ) else '0';
Y3 <= '1' when (A0='1' and A1='1' and A2='0' and g0='0' ) else '0';
Y4 <= '1' when (A0='0' and A1='0' and A2='1' and g0='0' ) else '0';
Y5 <= '1' when (A0='1' and A1='0' and A2='1' and g0='0' ) else '0';
Y6 <= '1' when (A0='0' and A1='1' and A2='1' and g0='0' ) else '0';
Y7 <= '1' when (A0='1' and A1='1' and A2='1' and g0='0' ) else '0';
END behavioral;

[N1LAF]

In the C:\projects\FPGA\Decoder\stimulus folder, right click, and create new text file, called decoder_tb.vhd

Copy the following into that file:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS

COMPONENT dec3to8g0 PORT(
Y0 : OUT std_logic;
Y1 : OUT std_logic;
Y2 : OUT std_logic;
Y3 : OUT std_logic;
Y4 : OUT std_logic;
Y5 : OUT std_logic;
Y6 : OUT std_logic;
Y7 : OUT std_logic;
A0 : IN std_logic;
A1 : IN std_logic;
A2 : IN std_logic;
g0 : IN std_logic
); END COMPONENT;


SIGNAL Y0 : std_logic;
SIGNAL Y1 : std_logic;
SIGNAL Y2 : std_logic;
SIGNAL Y3 : std_logic;
SIGNAL Y4 : std_logic;
SIGNAL Y5 : std_logic;
SIGNAL Y6 : std_logic;
SIGNAL Y7 : std_logic;
SIGNAL A0 : std_logic;
SIGNAL A1 : std_logic;
SIGNAL A2 : std_logic;
SIGNAL g0 : std_logic;

BEGIN

UUT : dec3to8g0 PORT MAP(
Y0 => Y0,
Y1 => Y1,
Y2 => Y2,
Y3 => Y3,
Y4 => Y4,
Y5 => Y5,
Y6 => Y6,
Y7 => Y7,
A0 => A0,
A1 => A1,
A2 => A2,
g0 => g0
);
-- testbench starts here --
tb : PROCESS
BEGIN

g0 <= '0';
A0 <= '0';
A1 <= '0';
A2 <= '0';

WAIT for 10 ns;
A0 <= '1';
A1 <= '0';
A2 <= '0';

WAIT for 10 ns;
A0 <= '0';
A1 <= '1';
A2 <= '0';

WAIT for 10 ns;
A0 <= '1';
A1 <= '1';
A2 <= '0';

WAIT for 10 ns;
A0 <= '0';
A1 <= '0';
A2 <= '1';

WAIT for 10 ns;
A0 <= '1';
A1 <= '0';
A2 <= '1';

WAIT for 10 ns;
A0 <= '0';
A1 <= '1';
A2 <= '1';

WAIT for 10 ns;
A0 <= '1';
A1 <= '1';
A2 <= '1';

WAIT for 10 ns;
g0 <= '1';


WAIT;
END PROCESS;
END;

[N1LAF]

In the LiberoSoC program, in the Design Flow box, expand "Create Design", right click on "Create HDL", and select "Import File"
Go to the \FPGA\decoder\hdl folder and select "decoder.vhd"

Under "Create Design", under "Verify pre-synthesized Design", right click on simulate, and select "Import File"
Go to the \FPGA\decoder\hdl folder and select "decoder_tb.vhd"


The decoder.vhd is our top level design file, and the decoder_tb.vhd is our testbench file, to test our design

After that is done, under "Verify Pre-Synthesized Design", and select "Open Interactively".

Dialog box: No testbench stimulus is associated with. Do you want to associate stimulus now? Click Yes.

Dialog box - Organize Stimulus files for dec3to8g0, in lower right, uncheck "Use default list from Project Manager"
Select the stimulus file, decoder_tb.vhd in the left box, and click on "Add ->". Click OK



Modelsim should run at this point. Waveforms on the right.
Under the "Wave" Window, scroll all the way to the left.

Right above the waveforms, there will be zoom controls, magnifying glass with a minus sign, keep clicking on that until you see all the waveforms change

[N1LAF]

Should see something like this:

http://paulfelgate.com/VHDL/modelsim_decoder.jpg

This is the POST-Synthesis simulation. The PRE-Synthesis simulation will not show the delta glitches as experienced by the POST-Synthesis. The glitches show what can/will do on changing inputs, and why clocking is important. We will get into clock schemes later, but what is important now is to get familiar with the interface,

[N1LAF]

LiberoSoC

http://paulfelgate.com/VHDL/LiberoSoC.jpg

[ab1ga]

Paul,

Installation almost complete here, but it's late enough for me to call it a night before I do something stupid. I'll pick it up tomorrow once my insides get warm and caffeinated.
How do you like the SoC version of Libero versus the old version?

73,

[ab1ga]

Dale reinstalls Libero, the play:

1. Reviewed the hardware kits available for different chip sets. Two kits cost $99, with a few bucks more for shipping:
- IGLOOnano starter kit
- SmartFusion starter kit

Igloo is simpler chip, basically just an FPGA, about 250k nominal gates, no real analog functionality
SmartFusion has ARM Cortex core on chip, and chip and board have more analog ability. Prices for these chips start at > $20 and go up to $50 range.

2. Decided to go with IGLOO kit, because anticipated projects may need analog function even SmartFusion chips can't provide, and chip cost is important. Also decided to download software support for IGLOO, ProASIC3 families, and SmartFusion chip families in case I want to get the other starter kit later.

3. Host system here is Windows 7 Home Premium, x64 flavor.

4. Registered for license file as described in earlier post. Received license.dat as email attachment. Copied that detachment to my desktop, NOT the final destination. Printed out the email with installation instructions. I never access email from an account with admin privileges, so attachments have to be moved in a two-step process. NOTE: Some software installations will allow a non-admin account to install software using a "sudo" like approach. This package doesn't. The first step completes, subsequent steps fail due to lack of administrator permissions. Easier to just do all the work in an admin account.

5. Logged into account with admin privileges. Created folder C:\flexlm and put the license.dat file there according to directions. Went to Control Panel / System and Security / System / Advanced Settings and added the three environment variables as described in the email, setting each to the location of the license file as directed.

6. Went to Microsemi site, choice between LiberoIDE 9.1 and LiberoSoC 10.0. Libero IDE is going to be used only to support legacy chips in the future, all new work will be done in LiberoSoC. Opted to install LiberoSoC 10.0, might as well learn the latest interface.

7. Multiple options for installation, HTTP download of an installer application, FTP of a ZIP file or an EXE file. I'm not interested in saving archives of old FPGA software, and the FTP downloads might need changes to Windows software policies, so the HTTP download was the way I went.

8. Downloaded 55Mb installer to Desktop, launched, and waited forever for download. When prompted with a product selection page, accepted defaults except for ModelSim, where I selected IGLOO, ProASIC3 families (4 of them), and the SmartFusion libraries. Waited for more download.

9. At the end, installer prompted to attach programmer hardware and click Next. Since I don't have a programmer yet (it's in the starter kit), I just clicked Next anyway, and the smoke stayed in the machine.

10. At completion, launched all of the component programs to make sure they were installed correctly. No problems. Onward and upward.

73 all,

[N1LAF]

Excellent recap, Dale, you are just about ready to dive into the VHDL/FPGA world.

When you start a new project, it really doesn't matter what device you select, select a mid-range device. This can be changed at any time, which is one of the flexibility of FPGA's. Just crunch it through like I did, and when you see the waveforms as I posted, you have succeeded, and ready to take on the world.


Updated comments: http://forums.hamisland.net/showthread.php?18823-The-FPGA-Forum-your-hosts-N9XR-and-N1LAF&p=402604&viewfull=1#post402604